Internatiooal Conference on Parallel Processing Shared Data Placement Optimizations to Reduce Multiprocessor Cache Miss Rates

Shared-memory multiprocessors with hardware coherent caches [1,4,6,7,10] are attractive in IIlat they can be programmed relatively easily and that they allow the program to take advantage of the caching of shared data. Recent studies have shown that shared clara may exhibit a high cache miss rate, especially if the parallelism is fme-grained [3,9). In large multiprocessors with considerable memory access latencies, a high cache miss rate may lead to poor machine performance. While optimizations that change the parallel algorithm or the data struc­ tures can greally modify the cache miss behavior, these optimizations often ~uire application knOWledge and user intervention. Here we focus only on the optimization of repositioning shared data at the cache block level. "The changes are all transparent to the programmer. This approaCh is motivated by the fact IIlat cache misses on shared data are often concentrated in small sections of the data space. Therefore, localized optimizations can potentially generate most of the desired effects. Figure I shows the cache misses on the shared data structures for one application. The average number of misses per byte for each data structure is computed by dividing the total misses on the data structure by the size of the data structure. The leftmost peak corresponds to an area of scalar variables and some small arrays.